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INTEGRATED CIRCUITS
SA9024 900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
Objective specification 1997 Aug 01
Philips Semiconductors
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
DESCRIPTION
This specification defines the requirements for a transmitter modulator and fractional-N synthesizer IC to be used in cellular telephones which employ the North American Dual Mode Cellular System (IS-136).
* Reference and clock buffers * Control logic for programming and power down modes
PIN CONFIGURATION
V CC GND MCLK V CC RCLK GND GND PHA PHI RN XTAL1 36 35 34 33 32 INA
FEATURES
* Low current from 3.75V supply * Low phase noise * Main loop with internal charge pump and fractional compensation * 3-line serial interface bus * Power down for the synthesizers * Speedup mode for faster switching
APPLICATIONS
48 47 46 45 44 43 42 1 2
41 40 39 38 37 XTAL2 TXEN DATA CLOCK LOCK STROBE GND V CC I I Q Q
PHP V CC
RXLO1 3 RXLO2 4 GND V CC 5 6
SA9024
31 30 29 28 27 26 25
* Cellular phones * Portable battery-powered radio equipment.
GENERAL DESCRIPTION
The SA9024 BICMOS device integrates:
TXLO1 7 TXLO2 8 GND 9
PHS out 10 Ipeak 11 TANK1 12
* Main channel synthesizer * Auxiliary synthesizer * Transmit offset synthesizer and oscillator * I/Q modulator * Power control
QUICK REFERENCE DATA
SYMBOL VCC ICC ICC_save fVCO fAUX fXTAL fPC Tamb PARAMETER Supply voltage Supply current Total supply current in power-down mode Input frequency Input frequency Crystal reference input frequency Maximum phase comparator frequency Operating ambient temperature Main and Aux loops VCC CONDITIONS
13 14 15 16 17 18 19 20 21 22 23 24 DUALTX1 DUALTX2 Vcc GND GND GND GND GND GND TANK2 GND Vcc
SR01536
Figure 1.
Pin Configuration
MIN. 3.6 - - 800 10 10 - -40
TYP. 3.75 TBD TBD - - - - -
MAX. 3.9 - - 1300 500 40 5 +85
UNIT V mA mA MHz MHz MHz MHz C
ORDERING INFORMATION
TYPE NUMBER NAME SA9024 LQFP48 PACKAGE DESCRIPTION Plastic low profile quad flat package; 48 leads; body 7x7x1.4 mm VERSION SOT313-2
1997 Aug 01
2
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
CONNECTIONS
MCLK
V
V
XTAL1
RCLK
GND
GND
GND
PHA
CC
INA
PHI
RN
CC
XTAL 2 PHP MAIN PD and CP V CC AUX. DIV. /A AUX PD and CP TX EN
DATA RXLO1 MAIN DIV. /N REF. DIV. CLOCK
RXLO2
GND
CONTROL LOGIC
LOCK
V CC
STROBE
GND TXLO1
V CC TXLO2 0 90 0 90
I
GND PHS out
I
/M
0 90 Q
Ipeak
TANK1
Q
GND
GND
GND
GND
GND
GND
TANK2
GND
VCC
DUAL TX1
DUALTX2
VCC
SR01455
Figure 2.
SA9024 Block Diagram
1997 Aug 01
3
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
PIN DESCRIPTIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 PIN PHP VCC RXLO1 RXLO2 GND VCC TXLO1 TXLO2 GND PHS OUT IPEAK TANK1 TANK2 VCC GND GND GND GND GND DUALTX1 GND DUALTX2 GND DESCRIPTION Proportional charge pump output Digital supply voltage Differential LO input Differential LO input Digital Ground Tank supply voltage Differential Transmit LO Input Differential Transmit LO Input Tank Ground Charge pump output (transmit offset) PHS out current set resistor VCO differential tank VCO differential tank Tx supply voltage Tx Ground Tx Ground Tx Ground Tx Ground Tx Ground Dual mode RF output Tx Ground Dual mode RF output Tx Ground 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 VCC Q Q I I VCC GND STROBE LOCK CLOCK DATA TXEN XTAL2 XTAL1 MCLK RCLK VCC PHA GND INA VCC GND RN GND PHI Tx supply voltage Inverting quadrature input Non-Inverting quadrature input Non-inverting in phase modulation input Inverting in phase modulation input Tx supply voltage Tx Ground Data input latch enable Lock detect Serial clock input Serial data input Transmit enable Crystal Oscillator emitter input Crystal Oscillator base Input Buffered oscillator output Buffered oscillator output REF supply voltage Auxiliary charge pump output REF Ground RXIF input CP supply voltage CP Ground CP current set resistor CP Ground Integral charge pump output
1997 Aug 01
4
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
OPERATING MODES & POWER DOWN CONTROL
There are two power saving modes of operation which the SA9024 can be put into, dependent on the status of the system. The intention of these different modes is to disable circuity that is not in use at the time in order to reduce power consumption. During sleep mode, only circuitry which is required to provide a master clock to the digital portion of the system is enabled. During receive mode, circuitry which is used to perform the receive function and provide a master clock is enabled. In transmit mode all the functions of the chip are enabled which are required to perform transmit, receive and provide master clock.
SA9024 POWER MODE TRUTH TABLE Sleep Mode Enabled Crystal Oscillator Phase detector and charge pump (transmit offset) VCO SSB Up-converter MCLK Buffer RCLK Buffer /M offset loop divider TXLO Buffer RXLO Buffer I/Q Modulator Variable Gain Amp. Control Logic Main Divider Reference Divider Auxiliary Divider Main Phase Detector and charge pump Auxiliary Phase Detector and charge pump Lock Detect yes no Receive Mode yes no Transmit Mode yes no
1997 Aug 01
5
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER MIN. VCC VIN PN TJMAX PMAX IMAX TSTG To Supply voltage Voltage applied to any other pin Power dissipation, TA = 25C (still air) Operation junction temperature Power input/output DC current into any I/O pin Storage temperature Operating temperature -10 -65 -40 -0.3 -0.3 VALUE MAX. +4.5 VCC+0.3 980 TBD +10/+14 +10 +150 +85 V V mW C dBm mA C C UNIT
DC ELECTRICAL CHARACTERISTICS
VCC = +3.75 V; TA = 25C; unless otherwise stated. SYMBO L VCC PARAMETER Power supply range Sleep mode Standby mode ICC Supply current y Operating: full power analog Operating: full power digital DUAL1 I/I Q/Q VIL VIH TA VO OL VOH RN RIpeak VRN VIpeak Ipeak PHSgain Kf In-phase differential input Quadrature phase differential input Clock, Data, Strobe, TXEN Clock, data, strobe, TXEN Ambient temperature range Output voltage LOW Output voltage HIGH External resistor to ground External resistor to ground Regulated voltage Regulated voltage PHSOUT programming PHSOUT gain PD phase gain Charge pump output current error g versus expected current. Sink to source current matching Current output variation versus VPHX Charge pump off, leakage current VPH Charge pump voltage compliance3 Charge pump output current error g versus expected current. Sink to source current matching VPHS = VCC/2 6 Charge Pump Outputs (only PHS) Ripeak = 4.7 kW IO OPH IMATCH -15 15 -10 15 10 % % VPHX = VCC/2 VPHX in compliance range VPHX = VCC/2 RN = 7.5 kW Ripeak = 4.7 kW Ripeak = 4.7 kW Ripeak = 4.7 kW Transmit offset PLL in phase lock IO = 2mA IO = -2mA VCC - 0.4 6 75 7.5 4.7 1.23 1.3 0.26 24xIpeak 4.33 24 quiescent quiescent Input logic low Input logic high -0.3 0.7 x VCC -40 +25 52 VCC /2 VCC /2 0.3 x VCC VCC+0.3 +85 04 0.4 V V V V C V V kW kW V V mA mA mA/rad TEST CONDITIONS LIMITS MIN 3.6 TYP 3.75 2 17 95 mA MAX 3.9 UNITS V
Digital Outputs Lock
Charge Pump Current Setting Resistor Input; RN, RIpeak
Charge Pump Outputs (including fractional compensation pump, not PHS) RN = 7.5 kW IO OPH IMATCH -15 15 -5 -10 -10 0.7 "1 15 5 10 10 VCC - 0.8 % % % nA V
1997 Aug 01
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
Current output variation versus VPH VPH Charge pump voltage compliance
VPHS in compliance range
-25 0.5
25 VCC-0.5
% V
AC ELECTRICAL CHARACTERISTICS
VCC = +3.75 V; TA = 25C; unless otherwise stated. SYMBOL Modulator TXLO 1/2 O/ VSWR TANK1/2 /M XTAL1 XTAL2 XO RCLK, MCLK TXEN Q/Q I/I TXRF DUALTX DUALTX VCO tank differential inputs PLL offset divider Osc. transistor base Osc. transistor emitter Negative resistance Reference buffer output Frequency range Output levels Harmonic content Transmit enable ZLOAD = 5k| | 7 pF 10 0.7 Transmit enable Transmit disable Maximum frequency Diff. mod. level Diff. input impedance DC bias point 1.8 0.8 10.0 1.8 820 AMPS/DAMPS Output level (avg. min., I and Q quad., 0dB VGA) Gain flatness 3rd-order 5th-order 7th-order VGA = 0dB VGA = -38dB 820 +6.0 +10 1 -42 -55 -65 -45 -33 -45 2 to 284 MHz 824 to 849 MHz DUALTX Spurious output 849 to 869 MHz 869 to 894 MHz 894 to 8490 MHz TXLO Upper Side Band DUALTX TXLO up-conversion products u -conversion roducts TXLO 3 x TXOFFSET Harmonics 10th DUALTX DUALTX DUALTX Broad-band noise (0dB VGA or +6 dBm, whichever is less) Adjacent channel noise power Alternate channel noise power 869 to 894 MHz @ 30 kHz @ 60 kHz -30 -45 -53 -30 -32 -45 -47 -45 -104 -45 -21 -21 -36 -21 -123 95 -95 -101 dBm/Hz dBc/Hz dBc/Hz dBc dBm dBc dBc 1.0 TXEN = 1 TXEN = 0 0.9 VCC/2 1.0 2.55 920 853 +13.5 40 1.4 -10 MHz VP-P dBc Logic MHz VP-P k V MHz MHz dBm dB dBc dBc dBc Frequency range Maximum input frequency Osc. frequency Osc. frequency 90 180 10 10 -100 40 40 Transmit LO input ( (AC-coupled; 50 single-ended, 100 differential) Input power Frequency range -13 900 2:1 180 MHz MHz MHz MHz W -10 1100 dBm MHz PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNITS
Baseband in-phase differential inputs TXRF operating range DUAL output SE=1, TXEN=1 (with external matching) (50) Differential output, (DUALTX) open-collector, matched to 200 differential impedance Linearity worst case intermod. products (0dB VGA OR +6 dBm, whichever is less, I & Q in-phase) Carrier suppression (I & Q in quadrature) Sideband suppression (I & Q in quadrature)
DUALTX DUALTX DUALTX
1997 Aug 01
7
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
Synthesizer Main Divider fMMAX Input frequency range Input harmonics RXLO 1/2 Synthesizer LO input (AC-coupled; external shunt 50 single-ended, 100 differential) Input frequency RANGE Input harmonics fAMAX VINA fCLOCK tSU tH Input frequency RANGE Input harmonics Input signal amplitude Serial Interface Clock frequency Set-up time: DATA to CLOCK, CLOCK to STROBE Hold time: CLOCK to DATA CLOCK tSW Pulse width STROBE (B - D words) A word 30 30 30 30 1 ) tW f REF @ NREF ns 10 MHz ns ns No multi-clocking No multi-clocking Auxiliary Divider 10 -10 0.200 500 MHz dBc VP-P No multi-clocking Input power Reference Divider fRMAX 10 -10 40 MHz dBc 800 -10 -20 0 1300 MHz dBc dBm
1. Transmit mode @ 33% duty cycle. 2. The relative output current variation is defined thus: DIout/Iout=2x(I2-I1)/|(I2+I1)|; with V1=0.7V, V2=VCC-0.8V (see figure 3) 3. Power supply current measured with RX = 2100.54 MHZ, REF = 19.44 MHz, INA= 109.92 MHz, main phase detector bias resistor = 7.5 kW. Main phase detector reference frequency = 240 kHz, auxiliary phase detector frequency = 240 kHz. 4. Maximum and minimum levels guaranteed by design and random testing for temperature range of -40 to +85C. 5. Power is rated at I/Q input level of 0.9VPP.
1997 Aug 01
8
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
CURRENT I2
I1
V1
V2
VOLTAGE
I2
I1
SR00602
Figure 3.
Output Current Definition
1997 Aug 01
9
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
Functional Description Main Channel Synthesizer & Auxiliary Synthesizer
CLOCK DATA STROBE SERIAL INPUT + PROGRAM LATCHES
FMOD PD1 FB 1 INM1 MAIN DIVIDERS INM2 NMAIN 16
NF 3
FB
FRACTIONAL ACCUMULATOR
FDAC PD1 MAIN PHASE DETECTOR 2 8 NORMAL OUTPUT CHARGE PUMP FDAC
RN
PHP SM 2 NR PD1 + PD2 MAIN REFERENCE SELECT FDAC /2 /2 /2 8 INTEGRAL OUTPUT CHARGE PUMP PHI 8 SPEED-UP OUTPUT CHARGE PUMP
12
INR
REFERENCE DIVIDER
SA 2 AUXILIARY REFERENCE SELECT PD2 NAUX PD2 14 AUXILIARY PHASE DETECTOR 2
RN
AUXILIARY OUTPUT CHARGE PUMP
PHA
LOCK INA AUXILIARY DIVIDER
SR01112
Figure 4.
Synthesizer Block Diagram clocked into a shift register. When STROBE = H, the clock is disabled and the data in the shift register remains stable. Depending on the 2 or 3 address bits, data is latched into different working or temporary registers. In order to fully program the synthesizer, 3 words must be sent: A, B and C. The D word programs all other functions within the SA9024. Those functions are
Serial Programming Input
The serial input is a 3-wire input (CLOCK, DATA, STROBE) used to program all counter ratios, DACs, selection and enable bits. The programming data is structured into 24-bit words; each word includes 2 or 3 address bits. Figure [5] shows the timing diagram of the serial input. When STROBE = L, the clock driver is enabled and on positive edges of the CLOCK, the signal on DATA input is
1997 Aug 01
10
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
power control, /M (offset loop), SE (Tx offset loop synthesizer enable), DUAL mode, Sleep Mode 1 and Sleep Mode 2. The data for FDAC is stored by the B word into a temporary register. When the A word is loaded, the data in this temporary register is loaded together with the A word into the work registers to avoid false temporary main synthesizer output caused by changes in fractional compensation. The A word contains new data for the main divider. The A word is loaded into the working registers only when a main divider synchronization signal is active to avoid phase jumps when
VALID DATA CHANGE
reprogramming the main divider. The synchronization pulse is generated by the main divider when it has reached its terminal count, at which time a main divider output pulse is also sent to the main phase detector. This disables the loading of the A word each main divider cycle during maximum of (NREF / REF) seconds. Therefore, to be sure that the A word will be correctly loaded, the STROBE signal must be high for at least (NREF / REF) seconds. When programming the A word, the main charge pumps on output PHP and PHI are set into the speed-up mode as soon as the A word is latched into the working registers and remain so as long as STROBE is held high.
DATA
D0
D1
D21
D23 LAST CLOCK
D0 FIRST CLOCK
tSU
tH
CLOCK
tSU
tSU
STROBE CLOCK ENABLED-SHIFT IN DATA
CLOCK DISABLED STORE DATA
SR01447
Figure 5.
Serial Input Timing Sequence
1997 Aug 01
11
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
Table 1. Function Table
Symbol FMOD NF NMAIN NREF RSM RSA FDAC NAUX CP LD PD1 Bits 1 3 16 10 2 2 8 14 2 2 1 Function Fractional-N modulus selection flag: `0' = modulo 8 `1' = modulo 5 Fractional-N increment Main divider ratio; 512 to 65,535 allowed Reference divider ratio; 4 to 1,023 allowed, RSM, RSA = "0 0" Reference select for main phase detector Reference select for auxiliary phase detector Fractional compensation charge pump current DAC Auxiliary divider ratio; 128 to 16,384 allowed Charge pump current ratio select (see table 1) Lock detect output select (see table 2) PD1 = 0 for power down; shuts off power to main divider and main chargepumps, anded with PD2 to turn off ref. divider. PD2 = 0 for power down; shuts off power to auxiliary divider, and auxiliary charge pumps; anded with PD1 to turn off ref. divider. Power control (see note 3) /M, M = 6, 7, 8, 9 (see note 4) Transmit offset synthesizer on/off Transmit mode: `0' = DUAL Mode control, 1 = digital; 0 = analog Sleep mode 1 Sleep mode 2 2. On the rising edge of the strobe and with the address decoder output = 1, the contents of the input shift register are transferred to the working registers. The strobe rising edge comes one half clock period after the clock edge on which the MSB of a word is shifted in. 3. The PC bits are used for the power control function. Eight (8) bits of data allows for appropriate resolution of the power control. 00000000 = 0 dB: 11111111 = -45.9 dB (= 255 0.18). 4. The M bits are used to program the /M counter for integer values between 6 and 9. 00 = 6, 01 = 7, 10 = 8, 11 = 9. 5. The TM bit is used to put the SA9024 into DUAL mode operation. In DUAL mode (TM = 0). 6. The AD bit allows a reduction in the linearity of the DUAL output driver while in AMPS mode. 7. The SM1 bit is used to shut down the TXLO buffers. SM1 = 1, buffers on; SM1 = 0, buffers off. 8. The SM2 bit is used to shut down the RCLK buffer. SM2 = 1, buffer on; SM2 = 0, buffer off. 9. The SE bit turns on and off the offset loop synthesizer circuits. SE = 1, synthesizer on; SE = 0, synthesizer off. 10. The LOCK bits determine what signal is present on the LOCK pin as follows:
PD2 PC M SE TM AD SM1 SM2
1 8 2 1 1 1 1 1
Table 2.
Lock Detect Output Select* LOCK 00 01 10 11 LOCK Pin Function Main, auxiliary and offset lock condition Main and auxiliary lock condition Main lock detect condition Auxiliary lock condition
1. Data bits are shifted in on the the leading clock edge, with the least significant bit (LSB) first and the most significant bit (MSB) last.
*When a section is in power down mode, the lock indicator for that section is high.
1997 Aug 01
12
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
TXEN CLOCK DATA CLK D (2) Q TEMPORARY REGISTER VCC
R Q
WORKING REGISTER
SE R D RQ CLK Q (1) SYNEN
(2) D STROBE CLK Q Q
SR01449
Figure 6.
Transmit Offset Synthesizer Reset Circuit The address decoder for program word `D' ANDed together with the strobe is used to load the contents of the temporary register into the working registers. D flip-flop (3) is used to prevent multiple strobe and address pulses in the event the address decoder output toggles on garbage bits during the time the strobe remains in a `1' state. The temporary register is common to the transmit offset synthesizer, main channel synthesizer and auxiliary synthesizer.
In Figure 6, the falling edge of the strobe and address, inverted, toggles the Q output of flip-flop (1) to a `1' state, enabling the phase detector, VCO, divide by M, TXIF buffer and SSB up-converter. Approximately 80s after the synthesizer is locked, the TXEN signal (enabled = 1) turns on the modulator and variable gain amplifier. The rising edge of TXEN has no effect on SYNEN, however, the falling (rising inverted) edge toggles the Q output of D flip-flop (2) to a `0' state. This disables the synthesizer, modulator and variable gain amplifier. To insure that slow edges on TXEN do not cause improper operation, the TXEN is a Schmitt trigger design.
1997 Aug 01
13
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
TXen
STROBE
SYNen 80mS 6.67mS SR01538
Figure 7.
Transmit Offset Synthesizer Timing Diagram
1997 Aug 01
14
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
Data format Format of programmed data
LAST IN p23 p22 MSB p21 p20 SERIAL PROGRAMMING FORMAT ../.. ../.. p1 FIRST IN LSB p0
A word, length 24 bits
Last in Address
0 0
MSB fmod
Fmod 0
LSB
First IN Spare
Fractional-N
NF2 0 NF1 1 NF0 0 N15 0 N14 0 N13 1 N12 0
Main Divider ratio- Nmain
N11 0 N10 0 N9 1 N8 0 N7 0 N6 0 N5 1 N4 1 N3 0 N2 0 N1 0 N0 0 0
sk1
sk2 0
Default:
A word select Fractional Modulus select Fractional-N Increment N-Divider
Fixed to 00. FM 0=modulo 8, 1=modulo 5. NF2..0 Fractional N Increment values 000 to 111. N0..N15, Main divider values 512 to 65535 allowed for divider ratio.
B word, length 24 bits
ADDRESS 0 1 R9 0 R8 0
REFERENCE DIVIDER NREF
R7 0 R6 1 R5 0 R4 1 R3 0 R2 0 R1 0 R0 1
RSM
RSM 1 0 RSM 0 0
RSA
RSA 1 0 RSA 0 0 Fdac 7 x
FRACTIONAL COMPENSATION DAC
Fdac 6 x Fdac 5 x Fdac 4 x Fdac 3 x Fdac 2 x Fdac 1 x Fdac 0 x
Default:
B word select R-Divider Charge pump current Ratio Main comparison select Aux comparison select Fractional Compensation
Fixed to 01 R0..R9, Reference divider values 4 to 1023 allowed for divider ration. CP1, CP0: Charge pump current ratio, see table of charge pump currents. RSM Comparison divider select for main phase detector. RSA Comparison divider select for auxiliary phase detector. Fdac7..0, Fractional compensation charge pump current DAC, values 0 to 255. FDAC = 77 for best op MOD8.
C word, length 24 bits
ADDRESS
1 0 A13 0 A12 0 A11 0 A10 0
AUXILIARY DIVIDER NAUX
A9 0 A8 1 A7 1 A6 1 A5 0 A4 0 A3 1 A2 0 A1 1 A0 0
CP
CP1 1 CP0 1
LOCK
LD1 0 LD0 0 PD1 TXEN
PD
PD2 TXEN
SPARE
PD3 0 LOD 0
Default
C word select A-Divider Charge pump current Ratio Lock detect output
Fixed to 10 A0..A13, Auxiliary divider values 128 to 16384 allowed for divider ratio. CP1, CP0: Charge pump current ratio, see table fo charge pump currents. LD1 LD0 0 0 Combined main, aux. & offset loop lock detect signal present at the LOCK pin. 0 1 Combined main and aux. lock detect signal present at the LOCK pin. 1 0 Main lock detect signal present at the LOCK pin. 1 1 Auxiliary loop lock detect signal present at the LOCK pin. When a section is in power down mode, the lock indicator for that section is high. PD1=1: power to N-divider, reference divider, main charge pumps, PD1=0 to power down. PD2=1: power to Aux divider, reference divider, Aux charge pump, PD2=0 to power down.
Power down
1997 Aug 01
15
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
Table 3.
Main and auxiliary chargepump currents CP1 0 0 1 1 CP0 0 1 0 1 IPHA 1.5xlset 0.5xlset 1.5xlset 0.5xlset IPHP 3xIset 1xlset 3xlset 1xlset IPHP-SU 15xlset 5xlset 15xlset 5xlset IPHI_SU 36xlset 12xlset 0 0
NOTES 1. ISET = Vset/RN; bias current for charge pumps. 2. CP1 is used to disable the PHI pump. 3. Iphp_su is the total current out of PHP in speedup mode.
D word, length 24 bits
Address
1 1 0 PC7 PC6
Power Control
PC5 PC4 PC3 PC2 PC1 PC0
M divider
M1 M0
SE
SE
TM
TM
AD
AD
Sleep Mode
SM1 SM2 pai5
Test pa_current
pai4 pai3 pai2 pai1 pai0
Default:
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
D0 word select Output Power Control M Divider Offset loop power down DUAL mode select AMPS/DAMPS mode select TX buffers power down Test: pa_current:pai
Fixed to 110. PC7(msb)...PC0(Isb) Provides output power attenuation for DUAL mode amplifier outputs in 0.18 dB steps, Fx = 45.9 dB. 00 = 6, 01 = 7, 10 = 8, 11 = 9 SE Offset loop synthesizer power down, SE = 1 power on, SE = 0 power down (sleep mode). TM = 0 DUALmode AD = 1 DAMPS mode. AD = 0 AMPs mode SM1 TX Local oscillator buffers power down. SM1 = 1 power on, SM1 = 0 to power down. SM2 RCLK buffer power down. SM2 = 1 power on, SM2 = 0 to power down. TX test bits for controlling the current in the power amp. Should be 0 during normal operation.
1997 Aug 01
16
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
MODES OF OPERATION
There are two power saving modes of operation which the circuit can be put into, dependent on the status of the system. The intention of these different modes is to disable circuitry that is not in use at the time in order to reduce power consumption. During sleep mode, only circuitry which is required to provide a master clock to
the digital portion of the system is enabled. During receive mode, circuitry which is used to perform the receive function and provide a master clock is enabled. In transmit mode all the functions of the circuit are enabled which are required to perform transmit, receive and provide master clock. When the circuit is powered for the first time, it is in DUAL MODE SLEEP.
Mode Programming
Mode Mode Setting and BlockStatus (X = ON) TXEN PD1 PD2 SE->SYNen TM SM1 SM2 Main loop, Ndivider, RXLO buffer Aux loop, Adivider Rdivider Offset VCO, Mdivider RCL buffer MCL buffer, reference input DUALTX PA TXLO buffer, SSB up-converter I/Q MODULATOR, VGA Control Logic X X X X X Dual Mode AMPS Sleep 0 0 0 0 0 0 0 RX 0 1 1 0 0 0 1 X X X TX 1 1 1 1 0 1 1 X X X X X X X X X X PD1 PD2 PD1 .OR. PD2 SE (+delay) See SE->SYNEN diagram SM2 1 (always ON) (.not. TM) .and. TXEN .and. SM1 SM1 TXEN .AND. SM1 1 (always ON) Logic
Main Divider
The input signal on RXLO is amplified to a logic level by a balanced input comparator giving a common mode rejection. This input stage is enabled by serial control bit PD1 = 1. Disabling means that all currents in the comparator are switched off. The main divider is built up to be a 16-bit counter. The loading of the work registers FMOD, NF and NMAIN is synchronized with the state of the main counter to avoid extra phase disturbance when switching over to another main divider ratio as is explained in the Serial Programming Input chapter. At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented with NF. The accumulator works modulo Q. Q is preset by the serial control bit FMOD to 8 when FMOD = `0'. Each time the accumulator overflows, the total divide ratio will be NMAIN + 1 for the next cycle. The mean division ratio over Q main divider cycles will then be: NQ + NMAIN ) NF Q Synchronization is provided to avoid a random phase on the phase detector upon the loading of a new ratio and when powering up the loop.
Auxiliary Divider
The input signal on INA is amplified to logic level by a single-ended input buffer, which accepts low level AC-coupled input signals. This input stage is enabled if the serial control bit PD2 = `1'. Disabling means that all currents in the buffer and prescaler are switched off. The auxiliary divider is programmed with 14 bits and has continuous integer division ratios over the range of 128 to 16,384.
Reference Divider (Figure 8)
The input can be driven by a differential crystal input or an external TCXO. This input stage is enabled by the OR function of the serial input bits PD1 and PD2. Disabling means that all currents are switched off. The reference divider consists of a programmable divide by NREF (NREF = 4 to 1,023) followed by a 3-bit binary counter. The 2 bit SM determines which of the four output pulses is selected as the main phase detector signal. To obtain the best time spacing for the main and auxiliary reference signals, a different output will be used for the auxiliary phase detector, reducing the possibility of unwanted interactions.
1997 Aug 01
17
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
MAIN SELECT RSM = "00" RSM = "01" RSM = "10" RSM = "11" REFERENCE INPUT DIVIDE BY NREF /2 /2 /2
RSA = "11" RSA = "10" RSA = "01" RSA = "00" AUXILIARY SELECT
SR01440
Figure 8.
Reference Variable Divider
Phase Detectors (Figure 9)
The auxiliary and main phase detectors each consist of a 2 D-type flip-flop phase and frequency detector. Each flip-flop is set by the negative edge of the divider terminal count output pulse. The reset inputs are activated after a delay when both flip-flops have been set. This avoids non-linearity or dead-band around zero phase error. The flip-flops drive on-chip charge pumps. A pull-up current from the charge pump indicates the VCO frequency shall be increased while a pull-down pulse indicates the VCO frequency shall be decreased.
Current Settings
The IC has two current setting pins, RN and IPEAK. The active charge pump currents and the fractional compensation currents are linearly dependent on the current in the current setting pins. This current, ISET, is set by an external resistor connected between the current setting pin and VSS.
Auxiliary Output Charge Pumps
The auxiliary charge pumps on pin PHA are driven by the auxiliary phase detector and the current value is determined by the external resistor attached to pin RN.
1997 Aug 01
18
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
VDDA
"1" D INR REF DIVIDER R CLK R Q
P
P-TYPE CHARGE PUMP
"1" AUX/MAIN DIVIDER X D CLK Q N R
PH
N-TYPE CHARGE PUMP
GND
VSSA
INR
R
X
P
N
IPH
SR01451
Figure 9.
Phase Detector Structure With Timing on the main charge pump current and its level relative to the main charge pumps is set by an 8-bit programmable DAC. The timing for the fractional compensation is derived from the main divider. The current level based on the value of FRD, FDAC and ISET. Figure 10 shows the waveforms (not to scale) for a typical base.
Main Output Charge Pumps and Fractional Compensation Currents
The main charge pumps on pin PHP and PHI are driven by the main phase detector. The current value is determined by the current at pin RN. The fractional compensation current is linearly dependent
1997 Aug 01
19
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
REFERENCE R
MAIN M N N N+1 N N+1
VCO CYCLES DETECTOR OUTPUT
2 ACCUMULATOR CONTENTS
4
1
3
0
FRACTIONAL COMPENSATION CURRENT PULSE WIDTH MODULATION OUTPUT ON PHP, PHI
mA
A
PULSE LEVEL MODULATION
SR01454
Figure 10.
Waveforms for NF = 2; Fraction = 0.4 when the relative counter is disabled (PD1 = `0' or PD2 = `0') for the main or auxiliary counter, respectively.
Figure 10 shows that for a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. The fractional compensation current is derived from the main charge pump in that it will follow all the current scaling through external resistor setting, programming or speedup operation. For a given pump, |comp + |pump x Fdac x FRD 128 5 x 128
Functional Description of Offset Loop, Modulator and Power Control Transmit Offset Synthesizer
The transmit offset phase locked loop portion of the SA9024 design consists of the following functional blocks: reference oscillator, limiters, phase detector, /M, IF VCO and passive loop filter. Harmonic contents of this signal are attenuated by an LP filter. The output of the IF VCO is also divided by N and compared with the reference oscillator in the phase detector.
Where: Icomp is the compensation current, Ipump is the pump current, Fdac is the fractional DAC value and FRD is the fractional accumulator value. The theoretical value for Fdac would then be: 128 for Fmod = 1 (modulo 5) and 80 for Fmod = 0 (modulo 8). When the serial input A word is loaded, the output circuits are in the "speedup mode" as long as the STROBE is H, otherwise the "normal mode" is active.
Reference Oscillator
This Oscillator is used to generate the reference frequency together with an external crystal and varicap. The output is internally routed to three buffers and a phase comparator. It is possible to run the oscillator as an amplifier from an external reference signal (TCXO).
Phase Detector and Charge Pump
The phase comparator is used to compare the output of the divider with the reference. It provides an output proportional to the phase difference between the divided down VCO and the reference. This output is then filtered and used as the control voltage input to the VCO. The phase detector is a Gilbert multiplier cell type, having a linear output from 0 to (/2 /2), followed by a charge pump. The charge pump peak output current is programmable to 6.4mA via the use of an external resistor. A preliminary design analysis has been performed with the following loop parameters:
Lock Detect
The output LOCK maintains a logic `1' when the auxiliary phase detector ANDed with the main phase detector ANDed with Offset Phase Detector indicates a lock condition. During the Standby mode of operation when the offset loop is unlocked, (SYNEN = low - see figure 6), the offset phase detector lock output is forced to an on (locked) state so that the lock detect will give an indication of receiver lock. The lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than "1 cycle on the reference input INR. The LOCK condition is also fulfilled
1997 Aug 01
20
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
A lock detect signal is provided and ANDed together with lock detect signals from both the main channel synthesizer and auxiliary synthesizer. While in standby mode, the lock detect signal will be forced to a valid lock state so that the lock detect signal will indicate when the main and auxiliary phase detectors have achieved phase lock.
quadrature phase shift networks and a low pass filter. The SSB up-converter is used to reject the unwanted upper sideband that would normally occur during the up-conversion process.
I/Q Modulator
The quadrature modulator is an active Gilbert cell multiplier (matched pair) with cross coupled outputs. These outputs are then provided to the variable gain amplifier. When the in-phase input I = cos (t) and the quadrature-phase input Q = sin (t) (i.e., Q lags I by 90), the resulting output should be upper single sideband.
Divide by M
The /M is a 2-bit programmable divider which can be configured for ney integer divide from 6 to 9. The divider is used to convert the VCO output down to the reference frequency before feeding it into the phase comparator.
Variable Gain Amplifiers
The variable gain amplifiers are used to control the output level of the device, with a power control range of 45.9dB. The output stages are differential, matched from 200 to 50.
VCO
This oscillator is used to generate the transmit IF frequency between 90MHz and 180MHz. The VCO tank is configured using a parallel inductor tuning varactor diode. DC blocking capacitors are used to isolate the varactor control voltage from the VCO tank DC bias voltages.
Power Control
The power control range should be greater than or equal to 45.9dB, having a monotonically decreasing slope, with 0dB = +11.5 dBm nominal. Eight bits are available for power control programming. The top 6 bits (PC7 to PC2) provide coarse attenuation with .6dB step size accuracy. The bottom 2 bits provide fine attenuation with .18 dB step size accuracy.
SSB Up-converter and TXIF Buffer
The TXIF buffer provides isolation between the SSB Up-converter and the VCO output. The Single Sideband Up-converter (SSB) is an active Gilbert cell multiplier (matched pair), combined with two
+11.5 TOP 12 dB FINE STEP ACURACY
-3 POWER OUT (dBm nom)
MAXIMUM ACCUMULATED ERROR (NOT TO SCALE)
-15
-26 BOTTOM 25 dB COARSE STEP ACCURACY
-28
0
12
24
38
45.9
VGA SETTING (dB)
SR01453
Figure 11.
Power Control circuitry which is always on, while the third buffer (RCLK) is used as a clock for external digital circuitry which is not used in sleep mode.
Oscillator Buffers
There are three buffers for the reference signal, two of which are used to provide external reference signals. The internal reference signal is used for the main and auxiliary synthesizer reference. The second buffer (MCLK) is used as a master clock for external digital
LO Buffers
The LO buffers are used to provide isolation for the VCO and between the transmitter up-converter and channel synthesizer.
1997 Aug 01
21
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
1997 Aug 01
22
Philips Semiconductors
Objective specification
900 MHz transmit modulator and 1.3 GHz fractional-N synthesizer
SA9024
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96
Philips Semiconductors
1997 Aug 01 23

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